A presently known photocoupler for use in program controllers or other devices is provided with an output delay circuit for delaying the output therefrom until the input thereto is stabilized so as to eliminate an adverse effect of chattering (a phenomenon wherein make-and-break occurs repeatedly) that takes place at contacts of relays or other devices. As shown in FIG. 9, a light receiving section for obtaining the output delay includes a light receiving element (photodiode) 1, an amplifier 2, comparators 3 and 4, and a capacitor 5. Here, in FIG. 9, the reference numeral 6 represents a constant-current circuit; 7 is a transistor; and 8 represents a negative feedback resistor. All the other parts in the light receiving section except for the capacitor 5 are monolithically integrated.
In general, a delay time td.sub.2 for the output delay is given by: EQU td.sub.2 =C.times.Vref.sub.2 /i . . . (1),
where C represents a capacity of the capacitor 5; Vref.sub.2 is a reference voltage of the comparator 4; and i is a current released from the constant-current circuit 6. Here, it is preferable to have an appropriately longer delay time td.sub.2 so as to eliminate the adverse effect of chattering. In order to prolong the delay time td.sub.2, it is advantageous to make i smaller in its value according to the equation (1). However, taking account of accuracy and reduction of dispersion in the integrated circuit, the current obtainable therein is limited to several .mu.A.
For example, in order to obtain the delay time td.sub.2 of 1 ms, suppose that a reference voltage of the comparator 4, Vref.sub.2 =2 V and i=1 .mu.A, the capacity C of the capacitor 5 is needed to be 500 pF. It is impossible to provide such a large capacity for the integrated circuit since it will occupy too large an area to be integrated. Therefore, only the capacitor 5 is added to the integrated circuit from the outside. This results in such a drawback that it becomes difficult to provide compact and light-weight photocouplers for use in program controllers or other devices.
Additionally, FIGS. 12 and 13 show a concrete example of a product of single-packaged photocoupler. The photocoupler 40 (Product Code PC902: manufactured by Sharp Corp.) is an AC input type photocoupler suitable for program controllers, whose light-generating section and light-receiving section are housed in a single package. Two parallel light emitting diodes having a reverse polarity to each other are connected between terminals n.sub.1 and n.sub.2 as the light-generating section, and an AC input is supplied thereto. A terminal n.sub.8 is pulled up to a constant voltage, while a terminal n.sub.5 is connected to ground. An output of the photocoupler 40 is obtained between the terminal n.sub.5 and a terminal n.sub.7. Further, an external capacitor C.sub.EX is connected between the terminal n.sub.5 and a terminal n.sub.7 for delaying the output. The reference numeral 40a represents a voltage regulator.
Here, contemplating the above drawback, the present invention provides a circuit configuration for a compact and light-weight photocoupler wherein a greater delay time can be obtained without adding a capacitor from the outside. In the arrangement as illustrated in FIG. 10, when a light receiving element 10 receives light, the output voltage ef an amplifier 11 rises and if it exceeds a reference voltage generated by a reference voltage circuit 14, a comparator 12 releases a signal I having High.
On the other hand, in an output delay circuit 13 is found an exclusive-OR between outputs of the comparator 12 and a D-type flipflop (D-FF) circuit 21 by an exclusive-OR circuit 31 of an exclusive logic circuit 30. Here, upon receipt of the signal I, the D-FF circuit 21 releases a signal VI having a predetermined delay time applied thereto by the use of a signal V as a clock signal generated by a frequency divider 20. The signal VI is sent to the next stage by way of an output buffer circuit 22.
Further, a NOT circuit 32 generates a signal II by inverting the output of the exclusive-OR circuit 31. This signal II forms a set signal for a low-active RS-type flipflop (RS-FF) circuit 17. Moreover, an AND gate 19 finds an AND between a signal III released by the RS-FF circuit 17 and an output of an oscillator 18. The frequency divider 20 divides down the signal IV indicating the AND to form the signal V. A reset circuit 33 produces a reset signal according to the signal V, and supplies it to the RS-FF circuit 17.
FIGS. 11(a) through 11(h) show a timing chart for individual signals I through VI in the output delay circuit 13. As shown in FIG. 11(a), when the signal I rises from Low to High, the output of the exclusive-OR circuit 31 also rises from Low to High, since the output of the D-FF circuit 21 is Low. As shown in FIG. 11(b), the NOT circuit 32 thus generates the signal II that falls from High to Low.
As described above, since the RS-FF circuit 17 is low-active, the signal III rises from Low to High as shown in FIG. 11(c). Consequently, the AND gate 19 opens, and the output of the oscillator 18 forms the signal IV to be supplied to the frequency divider 20, as shown in FIG. 11(d). The frequency divider 20 generates the signal V whose frequency is divided down, for example, as is shown in FIG. 11(e).
Using the signal V as a clock signal, the D-FF circuit 21 releases the signal VI that rises from Low to High when the signal V falls from High to Low. Thus, in comparison with the signal I, the signal VI has a delay time of one-half the cycle of the signal V generated by the frequency divider 20.
Therefore, without adding a capacitor from the outside, the output delay circuit 13 makes it possible to obtain such a great delay equivalent to that of the prior art arrangement. Consequently, the light receiving element 10, amplifier 11, comparator 12 and output delay circuit 13 can be monolithically integrated to form a light receiving section, thereby achieving a compact and light-weight circuit for a photocoupler.
However, in the above output delay circuit 13, as shown in FIG. 11(g), when the signal V falls from High to Low, if the signal I is forced to Low due to noise, the signal VI is kept Low as shown in FIG. 11(h), thereby causing malfunction. Thus, there is a drawback in that the signal VI tends to be unstable due to noise.